Sophie Thibaut

Sr. Process Engineer
Tokyo Electron

Sophie graduated from INSA Toulouse in France with an M.S in Physics. In 2011, she started working for STMicroelectronics R&D in Crolles, France, as an etch engineer on gate first integration for 28nm technology node. She then joined the IBM Alliance in 2012 in Hopewell Junction, NY,and worked on BEOL metal hard mask open at 64nm pitch using LELE integration for 14nm node. After 2 years, she returned to Crolles to work in manufacturing where she was in charge of BEOL trench dielectric etch for 90, 65 and 55nm. In 2015, Sophie joined TEL in Albany, NY, to develop etch patterning applications, working on self-aligned pitch splitting techniques, such as SADP for gate mask definition. She demonstrated novel integration for SAQP and published her work at SPIE 2016 and 2017. In 2018, she developed a metal hard mask open with EUV lithography at 40nm pitch, and performed stack and aspect ratio dependency roughness analysis on 32nm pitch line and spaces (SPIE 2018). At EUVL 2018, she compared line roughness behavior using multi-patterning option vs EUV based lithography.

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