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Poster Session: Optimization Techniques for C-Bit Utilization on the ETS-364

The demand for reduced test cost will not be slowing down in the Semiconductor Industry anytime soon. Test costs can be reduced by a number of ways, but one commonality with all of these methodologies involves resource optimization on the tester itself. The ETS-364 C-Bit (or Utility Data Bit in the case of the iFlex) circuitry can be used as more than just a method to turn on/off a single Handler Interface Board (HIB) relay. Taking a step back and looking at how the C-Bits are designed reveals that the Test Engineer has access to a node which can be treated as either on open-drain/Hi-Z output (when the C-Bit is in the OFF state), or a hard short to GND (when the C-Bit is in the ON state). Categorizing C-Bits in the manner allows one to add additional circuitry such as pull-up/pull-down networks on their ATE boards without having to burn additional analog resources.
 

In addition to providing extra circuity, one can also optimize the use of the relays themselves. Certain configurations of Solid State Relays (SSRs) can be hooked up in such a way that a single data bit can control multiple positions of multiple relays. This could potentially double the amount of controllable relays on one’s board without the need for additional C-Bits. 


Lastly, if all else fails one can simply use the PCA9557PW IC to expand the available C-Bits on any HIB. This IC enables one to add a total of 6 C-bits to their HIB with minimal additional surface area being sacrificed.

Speaker

Alex Saenz

Alex Saenz

Test Engineer, Texas Instruments

Speaker