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How and When State-of-the-Art Si-Photonics Will Replace Chip-to-Chip Interconnect in VLSI

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Years ago, we used optocouplers to interface various boards or actuators. Today, we have transceivers capable of 100GbE to 400GbE and beyond; all in a small mechanical housing. With the increase of data flow for cloud computing and 5G, the industry is working to reduce cost, power, and enhance the capability of the high-speed transmission for short or long distances. The efficiency of the CMOS industry using silicon photonics leads to very small in package optical chiplets around the dice (using 3D structure, multi stacking, TSV). Therefore optical I/Os and digital logic are converging to offer disruptive architecture for chips but also for system level. In this workshop, we explore state-of-the-art of Silicon Photonics and look to the future with a debate to understand "When will silicon photonics supplant copper interfaces for VLSI and beyond for datatcom?"

  • Welcome Introduction: Alain Delpy, Business Development Manager Photonics and Imager, SOITEC
     
  • Enabling SiPh packaging features to unleash next gen C2C solutions in a Wild West World
    Dan Berger, Senior Director of Advanced Silicon Packaging, GLOBALFOUNDRIES
  • Transitioning to Integrated Optics
    Brad Booth, Microsoft COBO
  • Leveraging the Benefits of Co-Packaged Silicon Photonics to Meet Future Data Center/HPC Needs
    Seyedi Ashkan, Senior Research Scientist, Hewlett Packard Labs
     
  • Path to Co-packaged Photonic I/O for Large-scale Chip-to-Chip Interconnect
    Thomas Liljeberg, GM Photonic Integration, Silicon Photonics Product Division, Intel
     
  • Si-Photonics Market Perspectives: From Pluggable Transceivers to Co-Packaged Switches ASIC
    Eric Mounier, Fellow Analyst, Yole Developpement
     
  • Next-Generation Optical I/O for Multi-Tbps Applications
    Prof. Vladimir Stojanovic, Chief Architect, and Co-Founder, Ayar Labs