Scaling DRAM Beyond 1znm
As DRAM fabrication approaches closer to fundamental scaling limits after 1znm node, integrated device makers must find other solutions beyond the traditional approach of aggressively shrinking the memory cell array in order to achieve viable cost reduction benefits node over node. Even with new process, tools, and integration flow solutions, the trend for cell area shrinks has slowed down due to technical and cost challenges in achieving the required pattern integrity. These challenges include achieving sufficiently high access device drive current and storage node cell capacitance, and low worldline and bitline parasitics. With smaller cell array shrinks, more aggressive scaling in areas such as the pitch cells, or Sense Amplifier and Wordline Drivers regions, and peripheral circuits are required to enable the desired die shrinks. This requires innovations in CMOS devices and interconnect technologies which can increase array efficiency, power, and performance. This presentation will cover historical trends and key challenges and explore various options to extend the planar scaling path beyond 1znm.