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CMOS Scaling Towards 2nm

In this talk we will review the scaling challenges and opportunities to scale CMOS technologies down to 2nm. Area scaling requires new device architectures beyond finFET as well as BEOL integration innovations in order to provide the expected power-performance of various high end IC applications. As a result of a careful design-technology co-optimization we will show how Logic designs as well as SRAMs can potentially scale to the exteme level of integration expected at the 2nm technology node.

Speaker

Julien Ryckaert

Julien Ryckaert

Ph.D., Program Director, imec

Speaker