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Session 2.3 - Design for Test: Transmission Line Close Loop Design Concept for Serdes and RF Test Hardware

Moscone North Room 21 Wednesday, July 10
3:05pm to 3:30pm

Analytical approach to test hardware design and performance validation. Application of transmission line concepts for objective assessment of performance in frequency, time domain of printed circuit board and other signal path interconnects. Definition of performance budget using S-parameters and tdr impedance along the signal path. Designing measurement strategy, tooling development to ensure signal integrity is not compromise during performance measurement. This paper will show performance validation techniques of the physical hardware or device signal path as a function of different standards and signal pattern. Signal pattern such as CJPAT, K28.5, PRBS with data rates from 3G to 25G or higher. 

Hardware high speed signal path validation techniques independent of device performance. Transmission line characteristics and real world performance is ascertained before 1st silicon. Enable RF, SERDES test engineers to focus on the device bring up, and debug. 

Application of design and simulation tools for close-loop design for critical signal path. Ansys, ADS, Cadence Allegro, Mentor Graphics Hyperlynx for software tools. Hardware validation instruments include VNA(Vector Network Analyzer) Spectrum Analyzer, Scopes and specialized fixtures. Performance comparison of PCB design and VNA measured touchtone files.

This paper to present performance validation of Test Sockets, PCB traces, Support circuitry, specialized connectors and interfaces.  

 

 

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