Complexity of modern semiconductor devices presents significant challenges to the design engineer, test engineer and the design-for-test (DFT) engineer. At the same time, new silicon bring-up and time to market pressures are increasing. When first silicon comes out, the DFT and test engineer have to debug issues quickly and efficiently. This is currently hindered by a lack of standard communication methodology between DFT(EDA) and test(ATE). Bring up takes weeks when it should take days.
This presentation will describe a new standards-based (IEEE 1687) solution to this bring up challenge where the EDA/DFT tool (Mentor Tessent® SiliconInsight®) connects over the network to ATE tools (Teradyne UltraFlex and Advantest 93000). The interface, ATE-Connect™, is an api that leverages the TCP/IP protocol. A case study will be presented showing an IJTAG example. Characterization / calibration results of a simple ADC will be shown on both the Teradyne and Advantest ATE systems.