To take full advantage of Industry smart manufacturing capabilities, organizations must holistically evaluate their Digital Architecture - from intelligent edge computing to the entire supply chain.
There is a great sense of urgency in preparing the supply chain to enable HVM at advanced nodes. Industry standards on how defects are measured on various components and sub-components and on how these results are reported are severely lacking.
As we reach the limits of scaling geometries, this session will explore new ways to continue to increase system functionality while reducing cost and size.
With the increasing complexity of IC architecture, and the continuing evolution towards the need to control each circuit component down to the molecular level, it is becoming essential to define new and/or updated ways to detect, measure and eliminate sources of contamination, ultimately reducin
Current architectures using 2D packaging and interposer-based solutions may not be sufficient for future high-performance, high-data-bandwidth applications like Artifical Intelligence. A variety of new ideas like monolithic or nre-monolithic 3D, in-memory processing, neuromorphic and quantum ar
Co-hosted by the Electronic Packaging Society (EPS) of IEEE and the SEMI Americas Advanced Packaging Committee
From EDA tools to voice and image recognition, machine learning and AI are increasingly important for both the design and the design process. This session will explore the impact on applications and tools.
Session Partner: Quantum Economic Development Consortium (QED-C)
Our morning session focused on the disruptive electronics system landscape, and we will shift gears slightly for our afternoon session.
There is no doubt that MEMS and sensors are at the leading edge of double-digit growth in multiple consumer and commercial applications. They are the source of much of the buzz around Artificial Intelligence and Machine Learning.
With one IC manufacturer having announced it will delay using EUVL until 2021, and another major foundry pivoting away from 7nm, it seems reasonable to take a closer look at the state of advanced lithography and how recent news could impact deployment of different choices as the industry proceed
Co-presented by: SEMI, UC Santa Cruz and CITRIS & the Banatao Institute
While the industry continues the work necessary to scale down to 5nm and 3nm in the more traditional ways, there is also significant work being done on the kinds of “scaling” technologies that are needed to move forward, such as 3D ICs.