Logic CMOS Scaling for High Performance Computing - Device and Material Innovations for the Next Decade

TechTALKS Stage North Thursday, July 11
2:00pm to 2:25pm

Countless innovations have helped Logic CMOS scaling to march on relentlessly, keeping Moore’s law alive for more than three decades. IBM has a rich history of pioneering such innovations for high performance computing that include Silicon-on-insulator, Copper interconnects, Gate-first High-k technology, to name a few. More recently, the world’s only FinFET-on-SOI technology integrated with eDRAM was developed in our labs and powers the world’s fastest supercomputer SUMMIT. Apart from the SOI FINFET architecture, unique elements such as SiBCN low-k spacer and vertical fins were pioneered in this technology. However, the amount of innovations needed to continue the scaling has increased exponentially in recent years. Currently, IBM Research is spearheading the development of next-generation device architecture and the unique elements needed to power IBM’s high-performance chips for the next decade. Nanosheet Gate-All-Around (GAA) transistors developed in IBM Research @ Albany Nanotech is being adopted by chip manufacturers across the industry. We will review some of the unique innovations developed that made this technology possible. Material innovations in contact and wiring levels that are playing more critical roles in performance enhancement will also be covered. In addition, focus will be given to DTCO activity that is assuming a more essential role in technology definition. Finally, an overview of device architectures and other performance enablers in the pipeline beyond GAA devices to enable further scaling will be covered.

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