Recent CMOS scaling is enabled by not only “classical” gate & metal pitch scaling but also track height scaling (reduction of number of metal lines per standard cell). Track height scaling forces reduction of fin number per device and eventually single fin devices are necessary at N3 and beyond. Single fin FinFETs degrade circuit performance dramatically due to its poor drive current. Gate-All-Around (GAA) devices, especially stacked nanosheet devices, have drive current advantage in single fin device thanks to its lager effective width per footprint as compared to FinFETs, which makes GAA attractive device option for N3 and beyond. In addition to that, better electrostatics in GAA devices enables further gate length & pitch scaling than FinFETs. However, GAA devices need more sophisticated processes for parasitic capacitance & resistance reduction, replacement metal gate scaling and strain engineering.