The Global 3D Packaging & Integration Technical Committee develops standards for semiconductor devices, including processed wafers, chips, or multi-chip configurations to the next level of integration; either in single- or multi-chip configurations. The Committee will focus on items such as materials needed for 3D applications, including prime silicon and glass wafers, temporary and permanent bonding material, specifications needed for processed wafers and/or chips to enter an integration step, etc. In addition, materials related to the elements of, interconnection schemes, and unique packaging assemblies that provide for the communication link between device and packaging. Also included, will be the technologies for heterogeneous and other multi-chip packaging such as Fan-out/Fan-in Wafer Level Packaging, Panel Level Packaging, Three-Dimensional Stacking IC, device embedded packaging, and flexible electronics technology, and metrologies to support these 3D integration and packaging technologies.
Joint 3DP&I Bonded Wafer Stacks and Inspection & Metrology Task Forces
Thursday, July 11 | 10:30-11:30am
Panel Level Packaging (PLP) Panel Task Force
Thursday, July 11 | 1:00-2:00pm
3D Packaging & Integration (3DP&I) North America Technical Committee Chapter Meeting
Thursday, July 11 | 2:00-4:00pm