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Dynamic Margining Lowers Voltage and Energy in Real Time

Smart Design Pavilion Tuesday, July 09
3:05pm to 3:35pm

As energy is quadratically proportional to voltage, energy savings can be achieved with ultra-low-voltage operation. Minima dynamic margining enables any processor or DSP core achieve up to 15x energy savings while still meeting user-set performance requirements. Such a core can modify energy usage in real time in response to performance needs, process variations, or environmental conditions. Minima margining enables ultra-wide DVFS that allows operation from ultra-low (0.4-0.5V) to nominal voltage. Dynamic margining is a HW-SW solution that is grounded on netlist-level logic enhancements which are completely compliant with mainstream EDA tools and allows tuning for UW-DVFS in the whole vertical application.

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