While the industry continues the work necessary to scale down to 5nm and 3nm in the more traditional ways, there is also significant work being done on the kinds of “scaling” technologies that are needed to move forward, such as 3D ICs. Different chip makers will use whichever methodology matches their customers’ needs and makes economic sense. This session takes a look at the various ways the industry is getting more out of traditional, and not so traditional, scaling. Also covered will be some of the more exotic architectures that could very will be used as the industry goes from 5nm to 3nm, and beyond.
TechTALK: Traditional, and Not So Traditional “More Moore” Scaling
TechTALKS Stage North Thursday, July 11 1:30pm to 3:40pm
Do you want to attend this session? Register for SEMICON West.
Director of CMOS Device Scaling
Logic CMOS Scaling for High Performance Computing - Device and Material Innovations for the Next Decade
Veeraraghavan S. Basker
Senior Technical Staff Member and Manager, Advanced Device Integration
IBM Research @ Albany Nanotech
Johanna M. Swan
Intel Fellow, Director of Package Research and Systems Solutions, Components Research
Nondestructive and Economical Dimensional Metrology of 3D-IC Structures Using Through-Focus Scanning Optical Microscopy (TSOM)
Ravikiran Attota, PhD
TSOM Project Leader
National Institute of Standards and Technology