Advanced CMOS and memory technologies are becoming more structurally complex at an amazing rate. In Logic CMOS, just since 65nm, we have introduced embedded stressor source/drains, replacement high-k/metal-gates, FinFETs, complex multi-patterning schemes and many more structural innovations. NAND Flash has moved from conventional planar bit-lines to amazing 3D vertical bit-lines. DRAM continues (against all odds) to scale the bit-cell area, by burying the word-line, using amazingly high-aspect ratio capacitors and employing even more complex multi-patterning schemes. In all of these innovations, the semiconductor industry has taken effectively “top-down processing capabilities” from the planar era, and applied them to 3D structures, using surfaces (ie, sidewalls) that were not previously employed in devices. The next set of logic and memory innovations will certainly continue this trend, even employing the processes to use surfaces not-visible from top-down observation. Gate-All-Around (GAA) or Nanowire devices, for example, will have critical structural requirements underneath the device, representing a whole new paradigm of challenges both for metrology and process. Process enhancements, such as Atomic Layer Deposition (ALD) and Atomic Layer Etching (ALE) will be required. Metrology improvements from Optical Critical Dimension (OCD) and X-Ray measurement techniques (XRD, XRR, etc.) will be required. But the integrated complexity of these processes and patterning schemes will also drive a new era in advanced model-based process control that links the most advanced metrology and inspection results with the most advanced processes and equipment-level controls through feed-forward and feed-back control schemes.
Improved process yield in these advanced technologies will rely on the reduction of total process variation: tool-to-tool, lot-to-lot, wafer-to-wafer and across-wafer. Traditional process yield-ramp activity has been aimed at reducing the variation of all individual steps of the process. However, each of these individual processes and their associated control parameters have developed quite differently, resulting in unique opportunities to use some processes to compensate for uncorrectable variations arising from other processes. This improvement will not rely on static process adjustments, but on active control of many processes in real time. In order to deliver the control information for state-of-the-art processes on advanced device structures at the pace of manufacturing, high speed 3D process modeling is required. This 3D model will aggregate all of the measured variation from prior processing into a silicon-accurate prediction of the current state of the critical device structures on each wafer. Using computational methods to form this prediction on multiple critical design features at multiple locations on every wafer will enable a new level of feed-forward process control using the newest controls being deployed on process equipment today. This type of 3D model-based process control will be especially critical to the processes and structures where metrology is able to provide only partial information on the nature of variations, which is often the case in these advanced device structures of the next generation. Attendees at this discussion will gain an understanding of high-speed 3D process modeling and how model-based process control can be used to improve process yield of advanced semiconductor technologies