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A General Machine Learning Framework for Semiconductor Design-to-Process and Yield Optimization

Wednesday, July 12 4:00pm

A large variety of machine learning (ML) techniques are being deployed, at an accelerated pace, in an expanding set of application domains. Semiconductor IC design and manufacturing are also starting to see a number of ML applications, albeit of limited scope. The introduction of a general technical framework, based on Computational Learning Theory, is an essential enabler for the implementation of ML solutions across the design-to-silicon process chain.  Within this framework, the entire set of generalized Design Rules, silicon retargeting, Optical Proximity Correction (OPC), post-OPC verification (ORC) and mask manufacturing constraints (MRC) can be demonstrated to be in a learnable set. Two recent applications will be illustrated, using Motivo’s novel computational tool for the characterization and preventative removal of yield detractors (manufacturing hotspots) in IC physical layout designs.

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