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Packing or Stacking? How do we get to 3nm?

Thursday, July 13 3:20pm

As CMOS scaling continues node to node, new innovations and architectures are being introduced.  The migration from planar to FinFET transistors was the first step in the front-end-of-line to take devices to 3D to achieve greater power savings and performance gains. Looking forward to 3nm, the evolutionary change from FinFETs to horizontal gate all around (GAA) device architectures will enable migration from single layer channeled devices to 3D stacked channels for the first time, taking yet another step towards true 3D stacked devices.  Horizontal GAA devices further increase performance and reduce power per layout area, which can be traded for lower patterning complexity and cost per given layout.  The path to continue scaling of these devices is to stack higher in 3D.

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