Keeping up with scaling objectives of Moore’s Law at 7 nm and 5 nm requires more than just obeying process scaled design rules. There are significant IP reliability, yield and robustness challenges stemming from scaling to those limits that must be considered.
This session will discuss Synopsys’ strategies for developing robust 7-nm/5-nm IP for SoC integration. We will provide an overview of tradeoffs that are made in library architecture, electrostatics, leakage, layout patterns and manufacturability design practices. In addition, we will discuss checks to meet performance, power, area and reliability requirements at these advanced processes. An associated EDA design flow that optimizes SoC design for those architectures will also be addressed.