As semiconductor technology nodes scale towards 5 nm, there are acute difficulties in achieving interconnect scaling due to dimensionality, design, performance and reliability issues, and due to novel device architectures. This talk will discuss the key interconnect scaling strategies for the 5nm nodes. These strategies are often in conflict with each other, but must be co-optimized to determine the overall best definition.
For 5nm and future nodes, the ability of optical patterning dimensions to support the required line pitches is in doubt. Some current design methodologies do not emphasize wiring track reduction or additional wiring levels. The BEOL resistance and capacitance is a significant portion of the parasitic degradation of overall technology performance. BEOL resistance does not scale, due to exponential increases in Cu resistivity not compensated by decreasing Cu diffusion barrier thicknesses. Challenges for BEOL capacitance include integration issues which drive the effective dielectric constant higher than the modeled values. BEOL reliability is challenged by operation voltage requirements and by novel device architectures which strain electromigration and dielectric breakdown performance.
To mitigate these challenges, design methodologies are decreasing the number of wiring tracks in standard cell libraries and increasing the wiring levels to improve both performance and density. EUV lithography is replacing optical lithography to enhance design and performance, requiring fewer design rule restrictions, improved patterning tolerances, and enabling bi-directional metal and process simplification. Hardware teams will implement novel processes to enable recovery of partial resistance/capacitance scaling, and to support the increasing demands on interconnect electromigration and time dependent dielectric breakdown reliability. These patterning and process improvements are needed to support novel device architectures in technologies such as scaled FinFET and Stacked-Si-Nanosheets.