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Hyper Scaling to Continue Moore’s Law

Thursday, July 13 3:00pm

Integrated circuit scaling has always depended on some form of technology innovation to realize the Moore’s Law benefits of smaller area and lower cost.  The past two decades have seen the introduction of major inventions such as copper interconnects, strained silicon, high-k metal gate and FinFET transistors.  But recent technology generations have also experienced a significant growth in mask count and process complexity that has caused the cadence of introducing new generations to take longer than 2 years.  To address this challenge, Intel has adopted hyper scaling techniques on its 14 nm and 10 nm generations.  Hyper scaling is a strategy of taking bigger steps in terms of area scaling on each of these generations.  Longer technology development time combined with improved area scaling have kept these generations on the rate of improving transistor density by ~2x every 2 years.  A standard quantitative transistor density metric shows Intel’s 10 nm generation to provide ~3.7x density improvement compared to the previous 14 nm generation.  The additional strategy of developing enhanced versions of these technologies continues to provide intra-generational process+product improvements on roughly an annual basis.  Although recent generations are taking longer than 2 years to develop and prepare for high volume manufacturing, hyper scaling continues to deliver the promises of Moore’s Law for improved density, lower cost-per-transistor and improved performance/watt.

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