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Patterning Enablement of Lithography Scaling

Thursday, July 13 11:30am

A decade of innovations in patterning has been the key enabler of the relentless dimensional scaling of both logic and memory devices at the heart of the today’s technology revolution. The practical application of these innovations in the lithography space has enabled optical lithography to routinely operate near the threshold of its theoretical limits of resolution in high-volume production. Concomitant innovations in patterning, such as multiple spacer and multi-color pitch splitting, have been developed and are now routinely applied in high-volume manufacturing to enable scaling to continue while the industry simultaneously develops next-generation lithography. Next-generation lithography such as EUV provides new opportunities for holistic patterning solutions to address fundamental physical challenges in continued scaling.

The tradeoffs in cost, cycle time, and edge placement error of these advanced patterning innovations have reached a critical state as devices continue to scale far beyond the traditional Rayleigh criterion of optical lithography. A new paradigm of patterning integration is proposed to address these challenges. On-product overlay, critical dimension control, photon and photoresist stochastics, and other patterning integration needs create new opportunities for collaborative innovation across lithography, materials, etch, deposition, and clean. The role of these collaborative partnerships between research consortia, equipment suppliers, and leading-edge technology manufacturers to address these tradeoffs will be discussed.

 
 
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