IDMs face a variety of patterning approaches as they consider nodes 7nm and beyond. New 3D device architectures will require extensions to current self-aligned multi-patterning techniques and most likely, the introduction of EUVL. Of the many alternatives to consider, each patterning scenario requires special consideration to its economic viability and inherent technical challenges. Extending current techniques with existing process equipment is an obvious approach that minimizes risk and cost. With any multi-patterning scheme, EPE (edge placement error) is likely to emerge as the fundamental barrier to scaling and EPE control is crucial when these processes ramp to high volume manufacturing. This presentation highlights TEL’s recent developments in multi-patterning, selective deposition/etch techniques and self-aligned/bottom-up approaches.