As device sizes move well into the sub-10 nm regime, metrology is being pushed into the atomic measurement domain with three-dimensional resolution and measurement uncertainties in the picometer domain. Conventional CMOS scaling requires metrology that can determine geometries and materials composition at near-atomic scales in addition to electronic device and circuit characterization. Contending new architectures will also require knowledge of the precise distribution and type of atoms as these can substantially affect device performance. The solutions to these remarkable challenges are at various stages across the world with significant work needed to enable manufacturing metrology for future devices. The National Institute of Standards and Technology (NIST) is developing atomic-scale metrology techniques for atom-scale device technologies. Modern TEM techniques offer atomic resolution imaging for determining the location and thickness of layers and their materials composition. Atom probe tomography with its atomic layer and individual atom resolution is indispensable for augmenting the accuracy and deconvolution of the robust but simpler SIMS data. Accounting for the underlying physics of signal generation through modeling is integral to improved optical and scanning electron microscopy methods. Optical and x-ray scattering techniques have led to major improvements in nanoscale characterization. Many of these methods can be combined and enhanced by using hybrid metrology techniques pioneered by NIST to achieve better measurement results and ensure lower uncertainties. By improving and quantifying the suite of metrology methods, industry will be able to better optimize the inherent tradeoffs among measurement cost, throughput, degree of destruction, resolution, and limitations to the bounds of a needed measurement result at the atomic scale. The future metrology methods, materials, and device technologies are increasingly interdependent on each other and to reach the fundamental limits will require a concerted effort that correlates detailed atomic scale information, electronic behavior and device performance in both development and manufacturing friendly environments.