IEEE/CPMT Workshop on:
“THIN IS IN": Thin Chip & Packaging Technologies as Enablers for Innovations in the Mobility Era

 

Presented by:

 

CPMT           IEEE

 

Tuesday, July 9, 2013
1:30pm-4:45pm
San Francisco Marriott Marquis

 

Session Chairs: Rolf Aschenbrenner, Fraunhofer IZM, Berlin

                        Jie Xue, Cisco, San Jose


Electronic products, such as smart phones, tablets and other consumer products drive the overall trend of maximum functional integration in the smallest and thinnest package with lowest packaging costs. One of the key technologies to achieve these goals is thin 3D-packaging. Developments have lately been made with various embedding technologies, such as Fan out WLP and embedded devices. Higher integration levels and lower profiles are also achieved with wafer-level processes, at which most R&D is concentrated in the commercialization of 2.5D IC´s (with silicon interposer) & 3D ICs, as well as coreless substrate. Furthermore, there is tremendous pressure to decrease overall package height even with the additional dies stacking through innovation in wafer thinning, TSV, and ultrathin interconnects.

 

In this workshop, leaders from key segments of the eco-system will share their perspectives and experiences on what the future directions and emerging opportunities in the “Thin Packaging Technology” area will be and their readiness for commercialization.

 

Agenda

 

1:30pm–1:40pm     

Welcome Remarks

Rolf Aschenbrenner, Fraunhofer IZM

Jie Xue, Cisco Systems

 

1:40pm–2:00pm

Packaging Technology Challenges for Mobile Computing Electronics

Mostafa Aghazadeh

Intel Corporation

 

2:00pm-2:20pm

Challenges for Thin Memory Packaging Technology

Nick (Namseog) Kim

S.K. Hynix

 

2:20pm–2:40pm

TSV-enabled 3D Memory Solutions

Scott Graham

Micron Technology

 

2:40pm–3:00pm

Break

 

3:00pm–3:20pm

Thin and Large Flip Chip Substrate

Koichi Nonomura

Kyocera

 

3:20pm–3:40pm

Performance of Embedded Packages Drives Thin is In

Johannes Stahr

AT&S

 

3:40pm-4:00pm

Enabling of Thin Packages by Fan-Out WLP

Jose Campos

Nanium

 

4:00pm–4:20pm

Thin Module Technologies

Ou Li

ASE Group

 

4:20pm–4:40pm

Thin Packaging Technology

Sung Yi

Portland State University

 

4:40pm-4:45pm

Closing Remarks

Rolf Aschenbrenner, Fraunhofer IZM

Jie Xue, Cisco Systems

 

5:00pm-6:00pm Reception

 

Reception Sponsors

 

Who Should Attend

 

Packaging, assembly and test technologists, including packaging and test engineers, designers and managers of package and test engineering teams

 

Registration

 

By June 7 After June 7
SEMI/IEEE Member $105 $150
Non Member $135 $150



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