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Semiconductor Test: Smarter, Faster, More Productive

Tuesday, July 9, 2013
North Hall, Moscone Center

                  Session Sponsor:



While some may be hopelessly waiting for a reduction in the capital cost of test equipment, most test professionals are exploring ways to improve test accuracy, increase overall equipment efficiency, better integrate ATE into the yield ramp and Total Quality Management systems, and solve difficult test problems in 3DIC and other new devices.  This session will explore the latest trends and developments to improve yield, advances in probe card technology, adaptive test integration, and 3DIC test.



1:30pm-1:55pm Test Data–A Key Asset for Effective Yield Learning
(Presentation in PDF)

Martin Keim, Ph.D.
Technical Marketing Engineer, Silicon Test Solutions

Mentor Graphics Corporation

Big Data Breakthrough at Top 5 Fabless Companies
(Presentation in PDF)


Danny Glotter (Biography)

CEO & Founder



New ATE Instrument for PCI-Express Protocol Testing
(Presentation in PDF)

Angarai Sivaram
Member, COE Group


Increasing Test Coverage and Speed with USer-Programmable FPGA's in Semiconductor ATE

(Presentation in PDF)

Luke Schreier
Senior Group Manager, Automated Test Platform Marketing
National Instruments


Quality in 3D Assembly: Is KGD Good Enough
(Presentation in PDF)

James Quinn
Vice President, Global Sales and Marketing
Multitest Electronics Systems

3:35pm-4:00pm Assembling the Wrong die! A Quality Issue in the Wings
(Presentation in PDF)

Charlie Weinberger (Biography)
Project Manager, Test Technology and Product Engineering Group
Texas Instruments
Session Moderator:
Ron Leckie (Biography)




Please check back frequently for updates and more information as agendas develop and speakers are announced.


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