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Semiconductor Test: Smarter, Faster, More Productive
Tuesday, July 9
1:30pm–4:00pm
North Hall, Moscone Center
| Description While some may be hopelessly waiting for a reduction in the capital cost of test equipment, most test professionals are exploring ways to improve test accuracy, increase overall equipment efficiency, better integrate ATE into the yield ramp and Total Quality Management systems, and solve difficult test problems in 3DIC and other new devices. This session will explore the latest trends and developments to improve yield, advances in probe card technology, adaptive test integration, and 3DIC test. |
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| 1:30pm-1:55pm |  |
Test Data–A Key Asset for Effective Yield Learning
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| 1:55pm-2:20pm |  |
Big Data Breakthrough at Top 5 Fabless Companies Danny Glotter (Biography) CEO & Founder
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| 2:20pm-2:45pm |  |
New ATE Instrument for PCI-Express Protocol Testing Angarai Sivaram (Biography) Member, COE Group Advantest |
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| 2:45pm-3:10pm |  |
Increasing Test Coverage and Speed with USer-Programmable FPGA's
Luke Schreier (Biography) |
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| 3:10pm-3:35pm |  |
Quality in 3D Assembly: Is KGD Good Enough James Quinn (Biography) |
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| 3:35pm-4:00pm |  |
Assembling the Wrong die! A Quality Issue in the Wings Charlie Weinberger (Biography) Project Manager, Test Technology and Product Engineering Group Texas Instruments |
Please check back frequently for updates and more information as agendas develop and speakers are announced.
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How to Register for this Program
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