Though progress to take EUVL into the realm of high-volume manufacturing continues to be made, the readiness of the source technologies to take on HVM are still not known with a high degree of certainty. The challenges facing source development are still average power, dose stability and uptime. EUV mask and resist infrastructure readiness activities must also come together in time and address such challenges as defect density (for masks), and line edge roughness, sensitivity, and resolution for resists. No doubt, there will be multiple opportunities to insert EUVL into lower volume production lines - such opportunities will be based on specific products and device applications. Until EUVL is ready for HVM, the industry must continue to rely on double-patterning and even multiple-patterning lithography schemes using 193 immersion lithography to take it beyond 22nm. Speakers will present the current status of EUVL readiness, as well as discuss the current plans and challenges of extending 193i with double and multiple-patterning.

Nikon Research Corporation of America

EUV Status and Outlook

Stefan Wurm, Ph.D.  (Biography)
Director of Lithography

SEMATECH

ASML

Advances in Directed Self-Assembly Integration and Manufacturability on 300mm Wafers

Ben Rathsack, Ph.D. (Biography)

Manager, CLEAN TRACK Advanced Technology Group,  Member of Technical Staff for the Semiconductor Production Equipment (SPE) Division

Tokyo Electron America

Collaboration to Deliver Lithography Solutions
 

Mike Rieger (Biography)

Group Director, R&D, Silicon Engineering Group

Synopsys

How to Register for this Program

I Have Not Registered for SEMICON West