Standards Technical Education Program (STEP): Wafer Edge Profile

July 12, 2011
1:00pm–5:00pm
San Francisco Marriott Marquis Hotel

 

 In many advanced wafer applications, a much tighter specification of the edge profile is required to control variations in subsequent circuit processing. These specifications frequently include values for certain characteristics that describe the segments of the edge profile contour. The relevant parameters used for characterizing the edge profile in more detail than in the past will be discussed in the program as well as the methods used for extracting them from measured edge profiles. These new parameters require a new format for specifying (the edge profile of) wafers, which will also be presented. Finally the importance of accurate edge profile characterization and specification for device processing and the anticipated requirements for future technology generations will be addressed.

 

Agenda

 

Sequence

Title and Speakers

Time
1

Introduction – Friedrich Passek

13:00
2       "New EP Specification Format in M1" - Peter Wagner, PWC
 13:10
3

"Parameter-based Test Methods for Edge Profile Characterization" – Murray Bullis, Materials and Metrology

13:30
4        "Benefit for Wafer Manufacturers and Customers when Aligning EP  Metrology  by Applying SEMI M73" - Stefan Bauer, Frank Riedel, Friedrich Passek, Siltronic
 14:00
5

"Overview on 450 mm Wafer Specification Activities Including EP Needs" – Mike Goldstein, Intel

 14:30
6

"Experimental EP Measurement for 300 and 450mm Actual Wafers using SEMI M73" – Hidehisa Hashizume, Masaru Akamatsu, Kobelco

 15:00
7

"SEMI M73 – EP Measurement Field Experiences" – Axel Gaglin, Thomas Becker, KoCoS

 15:30
8

"Edge Profiling as part of an overall strategy for edge inspection and metrology in IC" – Jennifer Kopp, KLA-Tencor

 16:00
10

 Panel Discussion and Conclusion 

    

 

Registration

 

by June 3

after June 3

SEMI Members

$150

$200

Non-members

$185

$200