Emerging Architectures for Logic and Memory

 

Tuesday, July 12

10:30am-12:30pm

NorthOne TechXPOT

     
Description

As the semiconductor industry prepares for the 15/14 nm node and beyond, technologists are facing a crossroads.   In this session, speakers will discuss materials and processes required to advance logic ICs and next-generation memory ICs.


During the logic session, speakers will describe the two main alternatives now being considered by the leading-edge logic makers: vertical devices (FinFETs), and fully depleted planar transistors based on extremely thin SOI (FD-ETSOI) substrates.  Another  presentation would look further out: moving from silicon channels to germanium and III-V materials in heterogeneous ICs.


Vertical transistors offer the potential for high performance, while presenting several manufacturing challenges. The transistors based on thin SOI substrates also have advantages and challenges. Can wafers with these thin layers be provided with consistent material thicknesses, at acceptable wafer costs? 


During memory portion of the session, researchers will detail several alternatives to today’s charge-based memories, including resistive RAMs (RRAMs), spin-torque transfer RAMs (STT-RAMs), and phase-change memories (PC-RAMs). Finally, memory companies are confident they can advance NAND flash chips by putting memory cells on top of each other. These cell array transistor (CAT) memories could link 16-32 memory cells, taking NAND well beyond the 20 nm generation.

 Logic  

 

 10:30am–10:45am

"FinFET Device Architecture for Sub-22nm Technology Nodes"

Presentation in PDF

Serge Biesemans, Ph.D. (Biography)

Vice President of Process Technology

imec

     
10:45am–11:00am  

Extremely-Thin SOI for Mainstream CMOS: Challenges and Opportunities

Presentation not available

Ali Khakifirooz, Ph.D. (Biography)

ETSOI Lead Device Engineer
IBM Research, Albany

     

11:00am–11:15am


Heterogeneous Integration of High Mobility Ge/III-V Channels on Si

Raj Jammy (Biography)

Vice President, Materials and Emerging Technologies

SEMATECH


     
11:15am–11:30am  

Question and Answer Panel

Moderated by: David Lammers, Editor-in-chief, SemiMD

     
Emerging Memory Types

 
11:30am–11:45am

"Metal-Oxide based RRAM Materials and Development"

Presentation in PDF

David Gilmer, Ph.D. (Biography)

Front End Process and Emerging Technologies

SEMATECH

     
11:45am–12:00pm

"Vertically Integrated Memory Process"

Presentation in PDF

Bart van Schravendijk (Biography)

Chief Technical Officer, Dielectrics and a Novellus Systems Fellow

Novellus

     
12:00pm–12:15pm  

Process Technologies Enabling Future NAND Flash Platforms

Gill Lee (Biography)

Senior Director

Applied Materials

     
12:15pm–12:30pm Question and Answer Panel

Moderated by: David Lammers, Editor-in-chief, SemiMD


     
 
   
   
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