Challenges Abound on the Technology Path to the 14/15 Node
By David Lammers, editor-in-chief, SemiMD
As the semiconductor industry prepares for the 15/14 nm node, technologists are facing several crossroads.
For logic ICs, the challenge — as Thomas Skotnicki of STMicro recently said — is that “conventional boosters are out of steam.” As the device pitch scales, there may be less benefit to strain techniques. Scaling the gate oxide thickness (Tox) is expected to be “very difficult,” according to Mukesh Khare, an IBM technology manager. Unless steps are taken, as copper interconnects shrink the line resistance will increase; and via resistance presents another interconnect challenge.
Memory chips face a related set of challenges. Kinam Kim, general manager of Samsung’s Semiconductor R&D Center, says that major scaling challenges face DRAMs and flash beyond the 20 nm generation.
The Emerging Architectures for Logic and Memory at SEMICON West will feature a two-hour discussion of the materials and processes being developed to deal with these challenges. The event will be divided into an hour-long discussion of the materials and processes required to advance logic ICs, and another hour on next-generation memory ICs.
During the logic session, speakers will present on two of the main alternatives now being considered by the leading-edge logic makers: vertical devices (FinFETs and other multi-gate MugFETs), and fully depleted planar transistors based on ultra thin body SOI (UTB-SOI) substrates. A third presentation would look further out: moving from silicon channels to germanium and III-V materials in heterogeneous ICs.
Vertical transistors offer performance and better electrostatic control, while presenting several manufacturing challenges. Avoiding excessive variability in the width of the fin, from the fin bottom to the fin top, is one issue. Finding room for the contacts is another challenge, and technologists must integrate stressors with these vertical devices.
The transistors based on ultra-thin-body SOI substrates also have advantages and challenges, which will be discussed during the TechXPOT. Researchers at the French research center CEA-Laboratory for Electronics & Information Technology (Leti) Leti have reported high performance with transistors built on a 6 nm layer of active silicon, on top of a 10 nm buried oxide (BOX) layer. Can wafers with these thin layers be provided with a) consistent material thicknesses, at b) wafer costs which are acceptable (the “value of performance” issue)?
Memory manufacturers are facing their own forks in the road. Researchers are working on several alternatives to today’s charge-based memories, testing a wide array of materials and designs. Resistive RAMs (ReRAMs) store bits by creating filaments when a voltage is applied to metal oxides. Some ReRAMs are non-volatile and could be embedded on logic wafers. Other ReRAMs are extremely fast and could provide a path beyond today’s DRAMs.
Research teams also are developing spin-torque transfer RAMs (STT-RAMs), which leverage the magnetic junction technology developed for magneto-resistive memories (MRAMs). And companies, including memory giant Samsung Electronics and flash vendor Numonyx, reportedly are putting samples of phase-change memories (PC-RAMs) into customers’ hands.
Finally, memory companies are confident they can advance NAND flash chips by putting memory cells on top of each other, a form of 3D stacking. These cell array transistor (CAT) memories could link 16-32 memory cells, taking NAND well beyond the 20 nm generation. R&D teams are working on vertical channel access transistor (VCAT) devices as well as planar structures.
Another hot topic to be addressed at SEMICON West is: Which lithography technology will be cost effective for 15 nm manufacturing? The industry appears to be hoping that EUV lithography will be ready for the critical layers. At the same time – to borrow a phrase from Sam Sivakumar of Intel – it is “scrambling to figure out ways to extend” 193 nm scanners.
A two-hour Advanced Lithography TechXPOT will be divided into an hour on EUV lithography, followed by an hour on Extensions to 193 nm Lithography.
For EUV, one presentation will discuss the state of the laser-produced plasma (LPP) EUV source power modules, to be followed by an update on the discharge-produced plasma (DPP) source power modules. These two presentations will clarify how source power is defined, in order for the general community at SEMICON West to understand the most meaningful metrics used to quantify the source power.
An update on the EUV scanners being used for process development and prototyping will follow. Finally, a presentation on the Sematech-led mask inspection consortium, the EUVL Mask Infrastructure Partnership, will provide a progress report on the basic directions of the MIP effort. The presentation will detail the state of the art in the effort to make full-field, defect-free masks.
The second hour of the Lithography TechXPOT will consider several methods to extend 193 nm scanners. Source and mask optimization (SMO) will be discussed, with examples of how SMO has been deployed for today’s chips. If possible, the TechXPOT will include a discussion on pixelated masks.
A second presentation will look at double patterning techniques, including the uses of spacers, litho-etch-litho-etch (LELE), and line-end optimization. Efforts to contain the cost of double patterning will be emphasized. A third presentation from a device maker will detail its internal cost modeling, comparing EUV with extensions to 193 for consumer-use system-on-chip (SoC) products.
The Lithography TechXPOT will include discussions on cost effectiveness, including energy consumption, cost of operation, footprint issues, tool lifetimes, and risk-related challenges.
If you would like more information about these topics at the upcoming SEMICON West, attend the SEMICON West 2011 Programs Preview Webinar on March 3 at 10:00am (PST). To register, click here: MARCH 3 WEBINAR REGISTRATION
For more information on SEMICON West 2011, visit www.semiconwest.org.
March 1, 2011