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Design for Test - Presented by EDA Consortium
Wednesday, July 9, 2014
Moscone North, Hall E, Room 130

Product design and manufacturing complexities along with higher levels of product integration (SoC, SiP, Multi-Core, 3rd party IP/cores, 3DIC, FinFet Devices, etc) requires new Design for Test (DFT) data volume and test execution time reduction strategies and innovations for these next generation, most challenging pin-limited designs.


In this session, attendees will hear from both EDA and ATE experts on the DFT challenges and solutions available to include new DFT Scan, compression, and synthesis techniques as well as new DFT related industry standards (STIL, etc) as well as new business models (cloud based solutions). 


Welcome and Session Overview

Bob Gardner

Executive Director

EDA Consortium


Cloud Testing Services in DFT


Angarai Sivaram,  Biography

Business Development Manager, Cloud Testing Services

Advantest America



IP and DFT


Richard Slobodnik,  Biography

DFT Engineer




Efficient Testing of Hierarchical Core Based SOCs


Bassilios Petrakis,  Biography

Product Marketing Director

Encounter Test Product Family



10:25am-10:40am B R E A K 

Ensuring High Defect Coverage of FinFET Based Designs


Stephen Pateras,  Biography

Marketing Director Silicon Test

Mentor Graphics 



Advanced DFT Architechture for Future SOC Devices & Cost Optimizations


Amit Sanghani,  Biography

Sr. Director Hardware Engineering



ATE Solutions for the Mobile Device Data Tsunami


Greg Smith,  Biography

VP SOC Marketing

Complex SOC Business Unit



Closing Remarks

Bob Gardner

Executive Director

EDA Consortium

12:00pm-1:30pm STS Networking Lunch (Room 133)


Please check back frequently for updates and more information as agendas develop and speakers are announced



Register for a Day Pass and select one morning sesssion and one afternoon session offered for the day. Networking lunch is included. Save 25% and sign up for the STS package and attend one session in the morning and one session in the afternoon on Tuesday, Wednesday and Thursday.  


You can also just register for the Test Vision 2020 Workshop.


For more information about other STS Sessions, Click STS Sessions


        By June 6               Starting June 7        
Member (Day Pass)        $169         $199
Non Member (Day Pass) $199         $239
Member (STS Package) $380         $449
Non Member (STS Package) $449         $539

How to Register for this Program


Start a New Registration

Upgrade Your Existing Registration

Begin a new registration record and select this and any other programs you wish to attend during step 3. If you are already registered for SEMICON West, visit to log in to the Registration Resource Center.  Select "Agenda Builder" to add this program.
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