STS is brought to you by:
 
Design for Test - Presented by EDA Consortium
 
Wednesday, July 9, 2014
9:00am-12:00pm
Moscone North, Hall E, Room 130
 

Product design and manufacturing complexities along with higher levels of product integration (SoC, SiP, Multi-Core, 3rd party IP/cores, 3DIC, FinFet Devices, etc) requires new Design for Test (DFT) data volume and test execution time reduction strategies and innovations for these next generation, most challenging pin-limited designs.

 

In this session, attendees will hear from both EDA and ATE experts on the DFT challenges and solutions available to include new DFT Scan, compression, and synthesis techniques as well as new DFT related industry standards (STIL, etc) as well as new business models (cloud based solutions). 
Agenda  
 
9:00am-9:10am                                

 

Welcome and Session Overview

Bob Gardner

Executive Director

EDA Consortium

 
 
9:10am-9:35am

Cloud Testing Services in DFT

 

Angarai Sivaram,  Biography

Business Development Manager, Cloud Testing Services

Advantest America

 

 
9:35am-10:00am           

IP and DFT

 

Richard Slobodnik,  Biography

DFT Engineer

ARM

 

 
10:00am-10:25pm           

Efficient Testing of Hierarchical Core Based SOCs

 

Bassilios Petrakis,  Biography

Product Marketing Director

Encounter Test Product Family

Cadence

 

 
10:25am-10:40am B R E A K 
 
10:40am-11:05am

Ensuring High Defect Coverage of FinFET Based Designs

 

Stephen Pateras,  Biography

Marketing Director Silicon Test

Mentor Graphics 

 

 
11:05am-11:30am

Advanced DFT Architechture for Future SOC Devices & Cost Optimizations

 

Amit Sanghani,  Biography

Sr. Director Hardware Engineering

nVidia 


 
11:30am-11:55am

ATE Solutions for the Mobile Device Data Tsunami

 

Greg Smith,  Biography

VP SOC Marketing

Complex SOC Business Unit

Teradyne  

 
11:55am-12:00pm

Closing Remarks

Bob Gardner

Executive Director

EDA Consortium


 
12:00pm-1:30pm STS Networking Lunch (Room 133)
   

 

Please check back frequently for updates and more information as agendas develop and speakers are announced

Registration

 

Register for a Day Pass and select one morning sesssion and one afternoon session offered for the day. Networking lunch is included. Save 25% and sign up for the STS package and attend one session in the morning and one session in the afternoon on Tuesday, Wednesday and Thursday.  

 

You can also just register for the Test Vision 2020 Workshop.

 

For more information about other STS Sessions, Click STS Sessions

 

        By June 6               Starting June 7        
Member (Day Pass)        $169         $199
Non Member (Day Pass) $199         $239
    
Member (STS Package) $380         $449
Non Member (STS Package) $449         $539


How to Register for this Program

 

Start a New Registration


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Begin a new registration record and select this and any other programs you wish to attend during step 3. If you are already registered for SEMICON West, visit www.semiconwest.org/rrc to log in to the Registration Resource Center.  Select "Agenda Builder" to add this program.
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