Silicon Wafers – Future Standardization to Enable the Transition

Wednesday, July 10, 2013
2:30 PM to 5:30 PM
San Francisco Marriott Marquis

Room: Golden Gate C2-C3


Since 2008, SEMI has published seventeen 450 mm wafer standards, guided by customer requirements and supplier feedback. These specifications, covering wafers, carriers, and loadports, have enabled the industry to continue the development of equipment, materials, interfaces, and processes, but further standardization will be necessary for a successful transition to manufacturing on 450mm wafers. Speakers from Intel, G450C, and others will introduce some of these new concepts during this seminar.


Proposals discussed during this workshop will be considered for standardization by the SEMI Standards Advanced Wafer Geometry Task Force under the Silicon Wafer Committee and the SEMI Standards Facilities Committee.


Who Should Attend

  • - Fab managers and manufacturers
  • - Equipment and materials suppliers
  • - Lead and chief engineers
  • - Development engineers
  • - Equipment, software and service engineers
  • - R&D laboratories, consortia
  • - Supply chain management


Tentative Agenda

14:30 – 14:50 Mike Goldstein (Intel): Towards 450 mm Silicon Wafers
14:50 – 15:20
Pinyen Lin [Biography] (G450C): Notchless Wafer
15:20 – 15:50 Kwangwook Lee (G450C): New Edge Exclusion Proposal
15:50 – 16:20 Gerd Pfeiffer [Biography] (IBM): Wafer Geometry for Advanced Nodes
16:20 – 16:50 Hisashi Furuya [Biography] (SUMCO): Challenges during 450 mm Silicon Processing
16:50 – 17:20 Allen Ware [Biography] (F450C): 450 mm Facilities Planning;Les Marshall [Biography] (G450C): G450C Component Lift Program Update
17:20 – 17:30 Q&A


  • SEMI member: $50
  • Nonmember: $75

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