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Contemporary Packaging: Challenges and Solutions for 40nm and Beyond

 

Wednesday, July 13

10:30am-12:30pm

NorthTwo TechXPOT

Hosted by the SEMI Advanced Packaging Committee - Americas

     
Session Chairs

Tom Gregorich, CT Package and PCB Engineering, MediaTek Inc.

Rich Rice, Sr. VP of Sales, ASE

     
Description

Much has been written about emerging technologies for the 40nm fab node (and beyond), such as CU pillar FC, ELK compatibility and 3D TSV.  However, product-level applications for these technologies tend to focus on performance-driven market segments;  markets which are better able to fund technology development and can accept higher initial risk.  But what about market segments which account for up to 70% of our industry and which are driven largely by low-cost and low-risk?  Are cost-effective IC package solutions available for market segments such as handheld, consumer and automotive as they migrate to smaller silicon lithographies in search of cost reduction?  When faced with the decision to use an advanced fab node, will  these companies:

  • •    Change package interconnect technology?  (ie. AU wire bond to CU wire bond to solder flip chip to cu pillar flip chip…)
    •    Change package and PCB technologies?  (i.e. lead frame to laminate or laminate to ?)
    •    Change system architecture?  (i.e. integrate chipset to decrease I/O density)
    •    Adopt new technologies such as FO-WLP and TSV?  (i.e. use advanced package technology to solve the problem)
    •    Continue to use the existing fab node?  (i.e. pass on the new nodes and maintain the current course)
    •    Do something else?

In this forum, leaders from the electronics ecosystem will share their ideas and experiences in addressing this extremely important topic.

     
Agenda    
10:30am-11:00am           

"More with Less:  The Challenging Dynamics of Semiconductor Packaging"

Presentation in PDF

Keynote
Jim Walker (Biography)

Research Vice-President

Gartner

   
11:00am-11:30am  

"Contemporary Packaging:  Challenges and Solutions for 40nm and Beyond"

Presentation in PDF

Keynote
Sunil Patel (Biography)

Principal Member of Technical Staff

Package Technology

GLOBALFOUNDRIES

     
    Panelists
11:30am-11:35am  

Doug Yu, Ph.D. (Biography)

Sr. Director of Interconnect and Packaging,

TSMC

     
11:35am-11:40am  SEMI speaker

"Contemporary Packaging:  Challenges and Solutions for 40nm and Beyond"

Presentation in PDF

Mike Ma, Ph.D. (Biography)

Vice President, Research & Development

Siliconware Precision Industries Co., Ltd (SPIL)

     

11:40am-11:45am

 

 

 SEMI Speaker

Presentation not available

Fernando Chen (Biography)

Senior Director, Laminate Products & Technology Marketing

STATS ChipPAC

   

 

11:45am-11:50am  SEMI speaker

"Contemporary Packaging: Challenges and Solutions from the Perspective of a Fab-Lite Company"

Presentation in PDF

Andy Kovats (Biography)

Sr. Manager of IC Package Development

Atmel Corporation

     
11:50am-12:30pm   Panel Discussion
    Moderator:  Jim Walker, Gartner
     
 

 

     
     
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