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3D in the Deep Submicron Era
Wednesday, July 13
1:30pm-5:00pm
NorthOne TechXPOT
Hosted by the SEMI Advanced Packaging Committee - Americas
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| Session Chairs |
Jie Xue, Director, Technology & Quality, Cisco Systems Gamal Rafai-Ahmed, AMD Fellow, AMD |
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| Description |
3D is more than 3D IC, and more than just Moore’s Law scaling. The drive for 3D has spawned a whole ecosystem for TSV technologies from industry, academia and research institutes, to equipment and material suppliers. Silicon interposer (2.5D) based upon TSV has become an important technology in this first wave of 3D implementation. From high performance network systems and servers to laptops, tablets, mobile systems and game consoles, the silicon interposer represents an important effort in the 3D community.
Will silicon interposer be a temporary stop or a solid fork in the highway for 3D progression? What is the silicon interposer ecosystem including the middle end redistribution with Cu pillar? How should the industry tackle memory stack assembly with TSV? Is the industry infrastructure in place for high volume, cost efficient 3D implementation? What is the next step? Speakers at this session will explore these questions and advance discussions about the present and future of 3D technology. |
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| Agenda | ||
| 1:30pm-1:50pm |  |
Keynote (Industry Vision) "Industry Vision of 3D in the Deep Submicron Era" Vincent Tong (Biography) Xilinx |
| 1:50pm-3:00pm | Panel Session 1 : 2.5 D Si
Interposer Packaging Technologies and Supply Chain Co-moderators: Sitaram Arkalgud, Director of Interconnect, SEMATECH John Lau, ITRI Fellow, Electronics & Optoelectronics Labs, ITRI |
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| 1:50pm-1:55pm |  |
“Impact of 3D ICs with TSV is profound but complex and costly – is there a better way?” Rao Tummala, Ph.D. (Biography) |
| 1:55pm-2:00pm |
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"Key Challenges - 2.5D TSV Silicon Interposer Packaging" Ron Huemoeller (Biography) |
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| 2:00pm-2:05pm |
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"Back Side Integration and Supply Chain Challenges" Jonathan Greenwood (Biography) |
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| 2:05pm-2:10pm |  |
"A Perspective on Implementing 2.5D Technology for Networking ASICs" Murray Stillway (Biography) Packaging Technology R&D Manager, ASIC Products Division Avago Technologies |
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| 2:10pm-2:15pm |  |
"Moving IC Test in a New Direction" Stephen Pateras, Ph.D. (Biography) Product Marketing Director, Silicon Test Mentor Graphics Corporation
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| 2:15pm-3:00pm | Panel Discussion |
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| 3:00pm-3:15pm | Break |
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| 3:15pm-3:35pm |
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Keynote (Technology & Market) Jean-Marc Yannou (Biography) |
| 3:35pm-4:45pm | Panel Session 2: 3D Packaging Technology and Ecosystem Co-moderators: Hirofumi Nakajima, Senior Manager, Packaging & Test Technical Strategy, Renesas Steve Bezuk, Director of Engineering, Qualcomm |
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| 3:35pm-3:40pm |  |
"Difficult Packaging and Test Challenges for 3D Integration" Bill Bottoms, Ph.D. (Biography) |
| 3:40pm-3:45pm |  |
"Critical Aspects of 3D Integration" Rozalia Beica (Biography) |
| 3:45pm-3:50pm |  |
"3D Ecosystem - an OSAT Perspective" Calvin Cheung (Biography) |
| 3:50pm-3:55pm |  |
"Co-Integration Challenges of 3D-TSV and Advanced Devices" Eric Beyne (Biography) Scientific Director, Advanced Packaging and Interconnect imec |
| 3:55pm-4:00pm |  |
No presentation available Subramanian S. Iyer, Ph.D. (Biography) IBM Fellow and Chief Technologist Microelectronics Division IBM Systems and Technology Group |
| 4:00pm-4:45pm | Panel Discussion | |
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