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3D in the Deep Submicron Era

Wednesday, July 13
NorthOne TechXPOT
Hosted by the SEMI Advanced Packaging Committee - Americas
   Session Sponsor:
Session Chairs

Jie Xue, Director, Technology & Quality, Cisco Systems

Gamal Rafai-Ahmed, AMD Fellow, AMD


3D is more than 3D IC, and more than just Moore’s Law scaling. The drive for 3D has spawned a whole ecosystem for TSV technologies from industry, academia and research institutes, to equipment and material suppliers. Silicon interposer (2.5D) based upon TSV has become an important technology in this first wave of 3D implementation. From high performance network systems and servers to laptops, tablets, mobile systems and game consoles, the silicon interposer represents an important effort in the 3D community.


Will silicon interposer be a temporary stop or a solid fork in the highway for 3D progression?   What is the silicon interposer ecosystem including the middle end redistribution with Cu pillar? How should the industry tackle memory stack assembly with TSV? Is the industry infrastructure in place for high volume, cost efficient 3D implementation? What is the next step?  Speakers at this session will explore these questions and advance discussions about the present and future of 3D technology.


Keynote (Industry Vision)

"Industry Vision of 3D in the Deep Submicron Era"

Presentation in PDF

Vincent Tong (Biography)
Senior Vice President, Worldwide Quality & New Product Introductions


 1:50pm-3:00pm  Panel Session 1 : 2.5 D Si Interposer Packaging Technologies and Supply Chain
Sitaram Arkalgud, Director of Interconnect, SEMATECH
John Lau, ITRI Fellow, Electronics & Optoelectronics Labs, ITRI

“Impact of 3D ICs with TSV is profound but complex and costly – is there a better way?”

Presentation in PDF

Rao Tummala, Ph.D. (Biography)
Pettit Chair Professor
Electrical and Computer Engineering and School of Materials Science and Engineering, Georgia Institute of  Technology
Founding Director, Microsystems Packaging Research Center


 SEMI Speaker

"Key Challenges - 2.5D TSV Silicon Interposer Packaging"

Presentation in PDF

Ron Huemoeller (Biography)
Senior Vice President, Advanced 3D Interconnects
Amkor Technology



"Back Side Integration and Supply Chain Challenges"

Presentation in PDF

Jonathan Greenwood (Biography)
Senior Member of Technical Staff,  Technology & Integration GLOBALFOUNDRIES

2:05pm-2:10pm  SEMI speaker

"A Perspective on Implementing 2.5D Technology for Networking ASICs"

Presentation in PDF

Murray Stillway (Biography)

Packaging Technology R&D Manager, ASIC Products Division

Avago Technologies

2:10pm-2:15pm SEMI Speaker

"Moving IC Test in a New Direction"

Presentation in PDF

Stephen Pateras, Ph.D. (Biography)

Product Marketing Director, Silicon Test

Mentor Graphics Corporation







2:15pm-3:00pm  Panel Discussion
3:00pm-3:15pm  Break
 SEMI Speaker

Keynote (Technology & Market)

3D Technology and Market Perspectives, evolution of the market drivers and development of the infrastructure

Presentation in PDF

Jean-Marc Yannou (Biography)
Project Manager - Advanced Packaging, Wafer-level Packaging & 3D System integration

Yole Developpement
 3:35pm-4:45pm  Panel Session 2: 3D Packaging Technology and Ecosystem
Hirofumi Nakajima, Senior Manager, Packaging & Test Technical Strategy, Renesas
Steve Bezuk, Director of Engineering, Qualcomm                  

"Difficult Packaging and Test Challenges for 3D Integration"

Presentation in PDF

Bill Bottoms, Ph.D. (Biography)
Chairman and CEO
Third Millennium Test Solutions, Inc. (3MTS)
Chair, ITRS Assembly and Packaging Technical Working Group

3:40pm-3:45pm SEMI speaker

"Critical Aspects of 3D Integration"

Presentation in PDF

Rozalia Beica (Biography)
Global Director of 3D Interconnect Technology Transfer and Integration
Applied Materials


"3D Ecosystem - an OSAT Perspective"

Presentation in PDF

Calvin Cheung (Biography)
VP of Engineering


"Co-Integration Challenges of 3D-TSV and Advanced Devices"

Presentation in PDF

Eric Beyne (Biography)

Scientific Director, Advanced Packaging and Interconnect



No presentation available

Subramanian S. Iyer, Ph.D. (Biography)

IBM Fellow and Chief Technologist

Microelectronics Division

IBM Systems and Technology Group

4:00pm-4:45pm   Panel Discussion



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