North Hall

Session Sponsor:

As the industry moves into implementation of deep submicron semiconductor technologies – 32nm to 28 nm with fragile low k dielectric materials – the issues connected with chip-package-interactions (CPI) are becoming prominent.  How can the physical stresses from the package (flip chip and wire bond) be sustained in the die during processing and field operations?   In CPI, the collaboration between the wafer foundry and IC package design and assembly, and system application are becoming increasingly significant.   What are the technical issues and solutions for different applications? In this forum, we have brought together leaders from the electronics ecosystem to share their ideas and experiences in addressing this extremely important topic.

2:00pm–2:25pm

Keynote: Complex Challenges and Innovative Solutions for Deep Submicron
(Presentation in PDF)
Bill Bottoms, Chairman and CEO
Third Millennium Test Solutions (3MTS)

2:25pm–2:50pm

Present and Future Challenges from Thermomechanical Prospective Beyond 45nm
(Presentation in PDF)
Gamal Refai-Ahmed, Ph.D. (Biography)
AMD Fellow
Advanced Micro Devices

2:50pm–3:15pm

Opportunities and Challenges in Deep Submicron IC Packaging – the FPGA Perspective
(Presentation in PDF)
Tarun Verma (Biography)
Senior Director, Packaging Engineering
Altera

3:15pm–3:40pm

Chip-Last Embedded Actives with 30um Pitch Interconnects in Ultra-Thin Organic Package
(Presentation in PDF)
Venkatesh Sundaram, Ph.D. (Biography)
Director of Research
Georgia Tech

3:40pm–4:05pm

Wafer Level Packaging: Trends and Challenges
(Presentation in PDF)
Dave Stepniak (Biography)
Manager, Wafer Level Packaging
Texas Instruments

4:05pm–4:30pm

William Chen
Senior Technical Advisor
ASE Group
(Presentation Not Available)

Session Moderator:

Paul Siblerud, Applied Materials