North Hall

Test Challenges

Even before the economic downturn, test strategies by IDMs and outsource testing firms were dramatically being transformed by new test methodologies, multisite test, BIST, test optimization techniques, increasing reliance on structural test and other new approaches. These new technologies, processes and methodologies are still being developed and evaluated and will emerge with force during the next upturn, potentially altering the landscape for test engineers, suppliers, and customers. This session will provide insights into the new test strategies and test challenges by leading device makers, experts and OSATS.

10:30am–10:50am

“Meeting the Economic and Technical Challenges of Wafer Test”
(Presentation in PDF)
Mike Slessor (Biography)
President and CEO
MicroProbe

10:50am–11:10am
 

“Meeting the Interface Challenge”
(Presentation in PDF)
Tom Bresnan
Sales Manager
R & D Circuits

11:10am–11:30am
 

“The Promise and Problems of Concurrent Test”
(Presentation in PDF)
Bruce Gravens
Field Engineer
Teradyne

11:30am–11:50am
 

“Test Considerations for Mobile Wireless Wafer Level Chip Scale Package (WLCSP) Applications”
(Presentation in PDF)
Adam Smith (Biography)
Wireless Center of Expertise Manager
Verigy

11:50am–12:10pm
 

“Balancing Cost and Capability”
(Presentation in PDF)
Len VanEck (Biography)
Business Development Manager
LTX-Credence

12:10pm–12:30pm
 

“Improved Cost of Test by Optimized Tester Utilization”
(Presentation in PDF)
Guenther Jeserer (Biography)
Business Unit Manager Volume
Multitest

Session Moderator:

Ron Leckie, INFRASTRUCTURE Advisors (Biography)