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SEMI / SEMATECH Presents: 3D Interconnect Challenges and Need for Standards Workshop

Media Partner

Event Code: 3DICSN
July 13, 2010
1:00pm–5:00pm
San Francisco Marriott Marquis

3D integration using TSV interconnects is creating many new challenges for the semiconductor industry. Metrology, overlay alignment, thin wafer handling and other TSV processes are among the list of concerns that are high priority for robust high volume manufacturing. As these solutions are implemented, a whole host of new problems may arise due to collision with our present equipment, materials and processes.

A key to the success and early adoption of 3D TSV manufacturing is improved factory productivity through standardized equipment, materials and processes. It is through this standardization that the industry can achieve the technological and economical goals of this emerging technology.

This workshop will provide the vision, progress to date, and solicit concern areas for 3D TSV integration, as well as identify the areas of variance between existing solutions and proposed/ anticipated solutions. It is anticipated that participants will also be prepared to share their thoughts and experiences dealing with TSV connected die and wafers.

Workshop Goals: In addition to technical exchange and constructive discussion and problem solving, the target is to identify one or several areas of standardization. At the conclusion, the goal is to identify participants willing to provide guidance and support with the development of new standards.

Agenda

Time

Topic

Speaker

1:00 – 1:10 PM

Moderator

Urmi Ray / Qualcomm

1:10 – 1:40 PM

Keynote: Adoption of 3D Integration Technologies through Standardization

Arifur Rahman / Xilinx

1:40 – 2:10 PM

Lessons Learned Applicable to SEMI 3D Standards

Andy Rudack / Sematech

2:10 – 2:40 PM

3D Interconnect Metrology Challenges for SEMI Standards

Vadim Mashevsky / Olympus

2:40 – 3:10 PM

Wafer Bonding Challenges

Bart Swinnen / IMEC

3:10 – 3:40 PM

Thin Wafer Handling

Ron Huemoeller / Amkor

3:40 – 4:10 PM

3D Via Hole Characterization

Chris Moore / Semilab

4:10 – 5:00 PM

Round Table Discussion

All

Click herefor speakers’ abstract and biography information.

Who should attend

3D TSV Engineers working in semiconductor Foundries, OSATS, IDMs, and Fabless companies. Suppliers of Process Tools, Metrology/Inspection Tools and Packaging Materials should also benefit from this workshop. All others interested in implementing standards related to 3D TSV bonded wafer processes

Registration

 

by June 3

after June 3

SEMI Members

$150

$200

Non-members

$185

$200

Due to the overwhelming interest in this program and the date quickly approaching, please register on-site at the registration desk on the GG level of the SF Marriott Marquis.

View Schedule of Events

Also see:

SEMATECH Second Workshop on Stress Management for 3D ICs using Through Silicon Vias, to be held during SEMICON West (July 13)

SEMATECH Workshop on 3D Interconnect Metrology, to be held during SEMICON West (July 14)

 
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